R&D Engineering, Principal Engineer

Principal Timing Signoff Engineer Principal Static Timing Analysis Engineer Principal Standard Cell Library Timing Engineer Principal STA Methodology Engineer Principal Library Signoff Architect We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent the better part of two decades chasing timing closure, and somewhere along the way you stopped thinking of signoff as a gate and started thinking of it as a prediction problem. You know that the difference between a library that works in a lab and one that ships in a million AI chips comes down to how well you modeled variation six months before tape-out. You have debugged enough customer escalations to recognize the smell of a characterization corner case, a parasitic extraction mismatch, or a setup check that looked fine until someone dropped VDD by 50 millivolts. You do not wait for perfect data. You work with what the foundry gave you, what the characterization team extracted, and what the customer is seeing in their design, and you triangulate toward truth. You have built signoff flows that other engineers actually use, not because you mandated them, but because they solve real problems. You can sit in a room with a characterization engineer, a customer's STA lead, and a foundry PDK owner and walk out with a plan that everyone believes in. At Synopsys, you will work on standard cell libraries that power some of the most advanced semiconductor designs in production today. The problems are hard, the nodes are bleeding-edge, and the work you do will directly affect whether a chip meets its performance target or not. What You'll Be Doing Own timing signoff methodology for standard cell libraries across TSMC N3, N2, N5, N7, and derivative nodes, defining setup, hold, recovery, removal, pulse-width, and noise margins that hold up in silicon Develop and validate multi-corner, multi-mode signoff flows for low-VDD, high-performance, and AI/compute SoCs, accounting for AOCV, POCV, SOCV, aging effects, and dynamic voltage drop Drive correlation analysis between Liberty models, PrimeTime STA results, HSPICE simulations, and silicon measurements to improve timing prediction accuracy and close signoff gaps Debug critical customer-reported timing issues, root-cause discrepancies between characterization, signoff, and deployment, and define corrective actions that prevent recurrence Build automation infrastructure in Python and Tcl to scale signoff validation, quality checks, and methodology deployment across multiple library releases Collaborate with characterization, CAD, modeling, EDA vendors, and foundry partners to influence signoff methodology direction and resolve advanced-node timing challenges Create technical documentation, best-practice guidelines, and deployment recommendations that internal teams and external customers rely on for signoff success The Impact You Will Have Your signoff methodologies will define how Synopsys standard cell libraries are validated and deployed across dozens of customer tape-outs on the most advanced nodes in production You will directly improve the accuracy of timing models that determine whether high-performance AI and compute chips meet their frequency, power, and yield targets Your correlation work will close the gap between what we predict in Liberty and what customers measure in silicon, reducing over-design margin and enabling better PPA You will resolve customer escalations that are blocking tape-out schedules, turning critical timing failures into understood, fixable methodology gaps Your automation and QA infrastructure will scale signoff validation