ASIC Physical Design, Staff Engineer

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years staring at timing reports that most people would find incomprehensible, and somewhere along the way you developed an instinct for what will break before it actually does. High performance memory IP like DDR, LPDDR, and HBM does not forgive sloppy timing closure, and you know that the difference between a design that ships and one that gets re-spun is usually a constraint you caught at 2am or a corner case you refused to ignore. You are the engineer who gets pulled into the room when timing looks impossible. Not because you have magic, but because you know how to read between the setup and hold violations, prioritize what actually matters, and script your way out of manual tedium. You have debugged asynchronous crossings enough times to know when a waiver is justified and when it is just wishful thinking. Automation is not a nice-to-have for you, it is how you stay sane. You write Python and Tcl scripts that do the repetitive work so you can focus on the hard decisions. At Synopsys, you will work on memory and SoC IP that powers some of the most performance-critical silicon in the industry, and the timing closure work you do will directly determine whether those designs meet their targets. What You'll Be Doing Close timing on high performance memory IP including DDR, LPDDR, HBM, and SoC designs across multiple process corners and operating modes Own static timing analysis from constraint development through final signoff using PrimeTime, PTECO, and DMSA Debug and resolve complex timing violations including asynchronous domain crossings, multi-corner convergence issues, and setup/hold trade-offs Implement engineering change orders to fix functional bugs and timing failures without destabilizing already-closed paths Build and maintain automation scripts in Python, Perl, Tcl, and shell to streamline STA workflows, report generation, and ECO implementation Collaborate with physical design, RTL, and verification teams across global sites to ensure timing, power, and area requirements are met Drive quality and efficiency improvements in the RTL2GDS flow by identifying bottlenecks and proposing tooling or methodology changes The Impact You Will Have Enable Synopsys memory and SoC IP to meet aggressive performance targets that customers depend on for next-generation products Reduce design re-spins by catching timing issues early and implementing robust constraint strategies that hold through tapeout Accelerate timing closure cycles across multiple projects by building reusable automation that eliminates manual, error-prone tasks Improve cross-functional alignment by translating timing analysis into actionable guidance for physical design and RTL teams Contribute to the quality and competitiveness of Synopsys IP portfolio through rigorous timing signoff and methodology discipline Mentor engineers on timing closure best practices, constraint development, and effective use of STA tools Shape the evolution of internal STA flows and tooling based on real challenges you encounter in high performance designs What You'll Need Bachelor's or Master's in Electronics Engineering, Electrical Engineering, Computer Science, or related field 5 to 9 years of hands-on experience in static timing analysis, with a focus on chip-level or IP-level timing closure Deep working knowledge of PrimeTime, PTECO, and distributed multi-scenario analysis tools Proven experience closing timing on high performance designs, ideally memory IP such as DDR, LPDDR, or HBM Strong scripting skills in Python, Tcl, Perl, or