Validation / Verification Eng, Staff Engineer

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have built a career designing and validating hardware systems that must perform reliably in production environments, not simply pass design rule checks. Your experience has taught you that schematic correctness is only the beginning; layout decisions determine whether signal integrity holds under real operating conditions. You work at the intersection of simulation and measurement. When analytical models diverge from bench results, you systematically identify which assumptions require revision. Years of routing high-speed interfaces have given you the expertise to anticipate common failure modes in JTAG chains and interpret S-parameter data with precision. Diagnostic work is central to your technical approach. You excel at distinguishing between silicon-level issues, PCB layout defects, and test environment artifacts. Your methodology is rigorous, your conclusions are defensible, and your recommendations are grounded in measured data. At Synopsys, you will validate memory interface IP where timing margins are measured in picoseconds and your board-level engineering directly determines product quality and customer success. What You'll Be Doing Design, layout, and validate printed circuit boards in Cadence Allegro for memory interface IP characterization and customer reference implementations Perform signal integrity analysis using S-parameters, eye diagrams, and crosstalk simulations to verify performance across multi-gigabit interfaces Debug hardware systems using logic analyzers, oscilloscopes, and protocol analyzers to isolate root causes across silicon, firmware, layout, and test configurations Conduct design reviews with cross-functional teams to establish best practices for routing, power distribution, and design constraint compliance Execute root cause analysis on validation failures to determine whether issues originate from silicon behavior, board design, or environmental conditions The Impact You Will Have Your board designs will provide the validation infrastructure for Synopsys memory IP deployed in automotive, mobile, and data center customer applications Your signal integrity analysis will inform design guidelines that reduce customer design iterations and accelerate time to market Your validation findings will provide critical feedback to silicon design teams, ensuring alignment between simulated and measured performance Your technical reviews will establish quality standards for layout evaluation and early detection of design issues Your diagnostic capabilities will reduce bring-up cycle times and expedite IP delivery to customers Your reference designs will serve as integration templates for customers implementing Synopsys IP in production systems What You'll Need Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or equivalent professional experience 6-8+ years of hardware design and validation experience focused on high-speed digital and mixed-signal systems Expert-level proficiency in Cadence Allegro for schematic capture, PCB layout, and constraint-driven design Comprehensive understanding of signal integrity principles including S-parameters, impedance control, crosstalk, intersymbol interference, and return loss Demonstrated experience debugging hardware using logic analyzers, oscilloscopes, vector network analyzers, spectrum analyzers, and protocol analyzers Working knowledge of communication interfaces including JTAG, I2C, SPI, and UART, with understanding of routing requirements and protocol-level diagnostics Who You Are You independen