Staff Engineer, Physical Design

Staff Engineer, Physical Design – PnR Implementation & Methodology We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You are an experienced Physical Design engineer with strong expertise in Place and Route (PnR) design implementation and flow methodologies . You have a comprehensive understanding of the complete PnR development flow and hands-on experience using industry-standard physical design tools such as Synopsys Fusion Compiler (FC) or Cadence Innovus . You understand physical design signoff methodologies and have exposure to tools such as IC Validator (ICV), RedHawk, PrimeTime, and StarRC , or equivalent solutions. Along with executing designs, you are interested in continuously improving implementation flows, methodologies, and Power, Performance, and Area (PPA) . You bring strong debugging, analytical, and problem-solving capabilities and are comfortable collaborating with cross-cultural, geographically distributed, and matrixed engineering teams. What You'll Be Doing Drive Place and Route (PnR) implementation for complex semiconductor designs. Execute and optimize physical design flows across key stages of the PnR lifecycle. Work extensively with Fusion Compiler (FC) and/or Innovus for design implementation. Perform and support physical design signoff using methodologies and tools such as ICV, RedHawk, PrimeTime, and StarRC , or similar. Analyze implementation results and identify opportunities for PPA improvement . Contribute to continuous improvement of physical design flows, methodologies, and flow usage . Debug complex implementation and flow issues using strong analytical and problem-solving skills. Collaborate with engineering teams across different functions, geographies, and cultures. Explore productivity improvements through modern engineering and AI-assisted tools such as Cursor . The Impact You Will Have Help deliver high-quality physical design implementation for advanced semiconductor designs. Improve Power, Performance, and Area (PPA) through design and flow optimization. Enhance the efficiency, robustness, and scalability of PnR implementation methodologies. Identify and resolve complex physical design and signoff issues. Contribute to continuous improvement and automation of implementation flows. Enable effective collaboration across global and cross-functional engineering teams. What You'll Need BS/B.Tech in Electrical Engineering (EE), Electronics & Communication Engineering (ECE), or equivalent with 5+ years of relevant experience , OR MS/M.Tech in EE, ECE, or equivalent with 3+ years of relevant experience . Strong hands-on experience in PnR design implementation and/or PnR flow methodologies . Comprehensive understanding of the PnR development flow . Good hands-on experience with Fusion Compiler (FC) or Innovus . Good understanding of physical design signoff tools and methodologies . Experience or exposure to ICV, RedHawk, PrimeTime, StarRC , or similar tools. Experience contributing to PPA improvement and flow optimization activities . Strong debugging, analytical, and problem-solving skills. Excellent collaboration and influencing skills with the ability to work effectively in cross-cultural, multi-geography, and matrixed teams . Exposure to AI-assisted engineering tools such as Cursor is a plus. Who You Are You approach complex physical design challenges methodically and drive them through resolution. You enjoy debugging implementation, timing, physical verification, and flow-related issues. You look beyond basic design closure and continuously seek opportunities to improve PPA and implementation efficiency .