ASIC Digital Design, Sr Staff Engineer

ASIC Verification Engineer, Staff We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, enabling everything from self-driving cars to advanced learning machines. As the global leader in EDA tools, semiconductor IP, and silicon engineering solutions, we empower the creation of the world’s most advanced chips across AI/ML, high-performance computing, automotive, cloud, and mobile applications. Within our division, we develop and deliver interface subsystems that power industry-leading SoCs. Join us to transform the future through continuous technological innovation and world-class engineering excellence. You Are: You are an enthusiastic engineer who thrives at the intersection of various interface IPs. Your analytical mindset and collaborative spirit drive you to solve complex technical challenges that shape the future of connectivity. You are passionate about deepening your expertise and excited by the opportunity to work on advanced DDR/HBM/PCIe/UCIe/Ethernet/UALink IP integration deployed in the most innovative SoCs. You value technical mastery, teamwork, mentorship, and the continuous pursuit of innovation. Your curiosity leads you to understand diverse interface IPs, and you ensure the highest standards of silicon performance through meticulous attention to detail. Navigating simulation environments and debugging challenging issues is second nature to you, and you excel at collaborating with teams across the globe. What You’ll Be Doing: Technically leading and driving ownership of critical areas of verification alongside a team of talented verification engineers. Defining, implementing, and tracking comprehensive verification test plans to ensure robust coverage and quality. Specifying, building, enhancing, and maintaining state-of-the-art Subsystem top-level UVM-based System Verilog testbenches, integrating RTL and behavioral models Coding and debugging test cases, including the creation of complex checkers and assertions using System Verilog/UVM. Extracting and reviewing functional coverage (FC) and code coverage metrics to ensure quality metric goals are met. Managing regressions and contributing to the continuous improvement of verification strategies and test environments. Debugging and resolving simulation failures, ensuring root-cause analysis and timely solutions. Working closely with RTL designers and architects to ensure functional correctness. The Impact You Will Have: Drive quality that powers AI, automotive, cloud, and mobile applications at massive scale. Advance the state-of-the-art in AI assisted verification methodologies, influencing future verification flows and processes. Contribute to the early detection and resolution of critical design issues, reducing time-to-market and silicon re-spins. Collaborate with a global team of experienced verification engineers, fostering knowledge sharing and professional growth. Bolster Synopsys' leadership in chip design by ensuring our IP verification methodologies set industry standards. What You’ll Need: Bachelor's or Master's degree in electronics/electrical engineering or related field, with 8+ years’ experience in ASIC/FPGA Verification. Ability to debug and define robust verification strategies; experience mentoring is a plus for senior candidates. Demonstrated experience in technically leading a team, record of successful collaboration and stakeholder management. Proven expertise in developing System Verilog/UVM based test environments for complex ASIC designs. Advanced skills in developing and implementing rigorous test plans, checkers, assertions, and coding complex tests. Strong proficiency in extracting and analyzing verification metrics such as functional coverage and code coverage. Experience with interface protocols and IP design/verification processes; knowledge of DDR/HBM/PCIe/UCIe/Ethernet/UALink is highly desirable. Hands-on experience in owning end-to-end