Analog Design, Principal Engineer

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent over a decade designing analog circuits that have to move data at speeds most engineers never touch, and you know that the difference between a SERDES that works in simulation and one that works in silicon is a hundred small decisions about layout, process variation, and timing handoff. You are the kind of engineer who reads a SerDes standard and immediately starts sketching architectures that push beyond what the spec requires because you see where the bottleneck will be two years from now. You do not wait for someone to tell you the PLL is the problem. You run the jitter budget, trace it back to the oscillator, and propose three solutions before the next design review. Taped-out circuits in FinFET nodes where a few femtofarads of parasitic capacitance can kill your bandwidth have taught you to work with layout engineers who understand that your redline is not optional. Presenting simulation data to a customer review panel and explaining why your adaptive equalizer architecture will handle their worst-case channel without adding another milliwatt is something you do comfortably. Mentoring matters to you, not because it looks good on a review, but because you remember the senior engineer who taught you how to read an eye diagram and you want to be that person for someone else. At Synopsys, you will work on Multi-Gbps SERDES IP that goes into chips that power data centers, automotive networks, and AI accelerators. The problems are hard, the process nodes are cutting-edge, and what you design will ship. What You'll Be Doing Review high-speed SerDes standards (PCIe, Ethernet, USB, CXL) and translate them into transceiver architectures and detailed sub-block specifications for Multi-Gbps NRZ and PAM4 designs Architect and design analog/mixed-signal circuits including TX drivers, RX front-ends, adaptive equalizers, PLLs, DLLs, bandgap references, regulators, oscillators, and ADC/DAC blocks for advanced FinFET and gate-all-around process nodes Collaborate with digital design teams on analog/digital co-design, calibration loops, adaptation algorithms, and timing handoff to ensure seamless integration and optimal performance Work directly with layout engineers to guide physical implementation, minimize parasitics, manage device stress and process variation, and ensure robust post-silicon performance Present simulation results, design trade-offs, and architectural decisions in internal reviews, customer meetings, and industry panel discussions Document design features, simulation methodologies, test plans, and characterization results, and support post-silicon bring-up and debug with electrical analysis and design iteration proposals Analyze customer silicon data and field performance to identify improvement opportunities and drive post-silicon design updates for next-generation IP releases The Impact You Will Have Define the architectural direction for Synopsys SERDES IP, influencing product roadmaps and enabling next-generation connectivity standards across automotive, data center, and AI markets Deliver power, performance, and area improvements that directly affect the competitiveness of Synopsys IP in advanced process nodes and high-speed communication applications Solve post-silicon challenges that unblock customer tape-outs and ensure successful deployment of Synopsys IP in high-volume production chips Mentor analog designers across the team, raising the technical bar for circuit design, simulation methodology, and design-for-reliability practices Strengthen Synopsys leadership in M