Staff ASIC Power Engineer, ML Accelerators

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As part of the TPU power design team, you will play a pivotal part in the improving power efficiency of our TPUs. You will drive power efficiency for our TPU designs, starting from building robust power models to proposing novel power optimization techniques. An ideal applicant would possess a deep background in modeling and optimizing chip power, as well as have an understanding of system level power considerations and tradeoffs. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits Learn more about benefits at Google . Contribute to design power modeling and drive convergence to power targets. Investigate, spec, and deploy architectural and microarchitectural power optimization techniques. Define best practices and methodologies to achieve low-power RTL designs. Collaborate with cross-functional software and system teams to create novel power management architectures to meet dynamic power targets. Own the execution and delivery of complex technical projects end-to-end, while being the technical lead of an experienced power team. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 10 years of experience in design or architecture (e.g., logic design, power architecture, performance, or SoC design). Experience with power design, power modeling, power architecture, or power reduction methodologies/techniques. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience defining and implementing chip-wide power management architectures and designs. Experience in power modeling, measurement, and correlation across the pre- and post-silicon phases. Experience with technical leadership and project ownership with a track record of successful delivery. Understanding of modern power and thermal management techniques at both the silicon and system levels (including Dynamic Voltage and Frequency Scaling (DVFS), Turboing, Thermal Management, and System-Level Tradeoffs). Ability to solve open-ended power and performance problems under ambiguity.