Analog design, Sr Staff Engineer

Alternate Job Titles Senior Staff Analog Design Engineer Staff Analog IC Design Engineer Senior Staff Mixed Signal Design Engineer Staff High Speed IO Design Engineer We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years designing analog circuits that do not just simulate cleanly, they work in silicon, under real conditions, with real noise and real margin pressure. You know that a CTLE that looks perfect in SPICE can still fail in a testchip if you did not account for substrate coupling or layout parasitics, and you are the kind of engineer who catches those issues before tapeout. You think in tradeoffs. Power versus speed. Area versus performance. Testability versus complexity. You do not need someone to hand you a perfect spec, you work with system architects and digital teams to figure out what the circuit actually needs to do, then you build it. When layout comes back with a question about metal stack or guard ring placement, you sit down and work through it because you know the circuit does not exist until it is drawn. Leading a design block or mentoring a junior engineer is part of how you work. You have done this long enough to know that the best designs come from teams that ask hard questions early. At Synopsys, you will work on high speed mixed signal PHYs that power AI, data center, and 5G applications. What You'll Be Doing Design analog circuits for high speed IO blocks (CTLE, FFE, TCOIL, DFE …) PLL, DLL, bandgap references, clock trees, and calibration circuits for UCIe and die-to-die PHY products Collaborate with layout engineers to ensure design intent translates into clean layout, then run post-layout verification to confirm performance holds Analyze and solve signal integrity, power integrity, noise, and margin issues across complex mixed signal systems Work with digital and system engineers to integrate analog blocks into full PHY designs and run mixed signal verification Design testchip architectures to validate circuits, then build test cases and run silicon bring-up in the lab to prove the design works in hardware Lead design reviews with global teams and mentor junior engineers on circuit design, layout collaboration, and verification The Impact You Will Have Your circuits will enable Tbps die-to-die connectivity in next generation AI accelerators, data center processors, and 5G infrastructure The design quality and margin you build in will determine whether products meet performance targets in production silicon Your collaboration with layout and digital teams will reduce iteration cycles and get products to tapeout faster The testchip architectures you create will de-risk new IP and give the business confidence to commit to new product roadmaps Your mentorship will build the next generation of analog design capability in the Vietnam engineering team Your work in the lab during silicon bring-up will close the loop between design intent and measured results What You'll Need BS, MS, or PhD in Electronics Engineering, Electromechanics, or Telecommunications 8+ years of hands-on experience designing high speed mixed signal PHY circuits with a track record of designs that have taped out and worked in silicon 3+ years leading design teams, managing projects, or owning full design blocks from spec to silicon Deep understanding of analog circuit design fundamentals including noise analysis, signal integrity, power integrity, and layout effects Strong English communication skills for presenting design reviews, writing documentation, and collaborating with global teams Experience with academic research or publishi