Applications Engineering, Sr Staff Engineer (Physical Verification)

We Are At Synopsys, we drive the innovations that shape the way we live and connect. Our technology powers the Era of Pervasive Intelligence, enabling breakthroughs in AI, high-performance computing, automotive, mobile, and cloud infrastructure. We deliver industry-leading silicon design, verification, IP, and software solutions that help customers bring innovative products to market faster and with greater confidence. Our Physical Verification Applications Engineering team partners closely with semiconductor companies, foundries, and internal engineering organizations to solve the industry's most complex signoff challenges. We develop advanced methodologies, drive technology adoption, and help customers achieve predictable design closure on the most advanced process nodes. You Are You are a seasoned Physical Verification expert with deep experience in signoff verification and semiconductor design methodologies. You understand that successful tapeout requires more than running verification decks. It demands technical leadership, scalable methodologies, automation, and close collaboration across multiple engineering disciplines. You thrive on solving complex DRC, LVS, ERC, Density, Antenna, and reliability verification challenges at advanced technology nodes. You are comfortable working directly with customer engineering teams, understanding their design bottlenecks, and driving solutions that improve productivity and accelerate design closure. You enjoy mentoring engineers, influencing technical strategy, and developing innovative verification methodologies that scale across projects and organizations. What You'll Be Doing Lead Physical Verification signoff activities for strategic Synopsys customers across advanced semiconductor technologies. Drive DRC, LVS, ERC, Density, Antenna, PERC, and Reliability Verification closure for large-scale SoC and custom design projects. Develop and deploy scalable PV methodologies, automation frameworks, and productivity-enhancing verification flows. Collaborate with Physical Design, Custom Design, Technology, Foundry, CAD, Product Engineering, and R&D teams to resolve complex signoff challenges. Analyze technical risks and proactively identify verification bottlenecks that may impact project schedules and tapeout milestones. Provide technical leadership and mentorship to engineering teams while promoting verification best practices. Support customer engagements by understanding design challenges and proposing innovative verification solutions. Drive feedback into Synopsys product development teams to enhance Physical Verification technologies and customer workflows. Influence roadmap decisions and adoption of next-generation verification methodologies for advanced process technologies. Contribute to customer success by improving verification turnaround time, design quality, and signoff predictability. What You'll Need B.Tech with 8+ years or M.Tech with 6+ years of experience in Physical Verification, Physical Design, or related VLSI domains. Strong expertise in Physical Verification signoff flows including: DRC LVS ERC PERC Density Verification Antenna Verification Reliability Verification Hands-on experience with industry-leading EDA tools such as: Synopsys IC Validator (ICV) Siemens Calibre Cadence Pegasus Or equivalent Physical Verification platforms Deep understanding of advanced semiconductor technologies such as 7nm, 5nm, 3nm, and beyond. Strong knowledge of: Semiconductor manufacturing processes Device physics Physical layout design Design-for-Manufacturing (DFM) Advanced process-node signoff methodologies Proven experience debugging complex PV violations and driving signoff closure across large-scale projects. Strong scripting and automation skills using Python, Perl, Tcl, Shell, or similar programming languages. Experience developing reusable methodologies, automation solutions, and verification process improvements. Exposure to cloud computing, distributed verification environment