ASIC Digital Design - Staff Engineer

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years learning that the hardest bugs to catch are the ones simulation will never hit, and you have built the muscle to prove they cannot happen at all. Formal verification is not a side skill for you, it is the primary tool you reach for when correctness matters more than coverage metrics. You know that a well-written assertion is worth a thousand directed tests, and you have debugged enough counterexamples at 3 a.m. to tell the difference between a real bug, a missing assumption, and a property that was just worded wrong. Reading RTL is second nature. You can look at a state machine or a FIFO controller and start sketching the properties in your head before anyone asks. When a proof will not close, you do not give up, you add a cut point, split the case, tighten the constraint, or abstract the helper logic until the engines can finish. You have worked with designers who trust formal and designers who do not yet, and you have learned how to bring both groups along. At Synopsys, you will own formal sign-off for real blocks that ship in customer silicon, and you will help build the next generation of verification engineers who think proof-first. What You'll Be Doing Own formal property verification end to end for assigned digital RTL blocks, from clocks and resets through proof closure and final sign-off Read design specifications and RTL to write SystemVerilog Assertions, assumptions, and cover properties that capture the intended behavior and legal input space Build and maintain formal testbenches including bind files, helper logic, abstraction wrappers, and constraint sets in SystemVerilog Run formal tools, tune solver engines and effort settings, and push proof bounds on hard properties until they close or you root-cause why they cannot Debug counterexamples to determine whether the issue is in the RTL, the property, or the constraint set, and work directly with designers to resolve it Apply targeted abstractions such as cut points, case splits, blackboxing, and over-constraints when a proof will not converge, then systematically relax them to restore completeness Review simulation testbenches and specifications to identify missing legal-input assumptions, and keep formal constraints aligned with how the block is actually used Track and report property status across proven, covered, falsified, and inconclusive buckets, and clearly communicate coverage gaps and open issues to the design and verification leads Mentor and guide recent graduate engineers on the team, helping them build practical formal verification skills and develop sound debugging instincts The Impact You Will Have Catch corner-case bugs before tapeout that simulation would never reach, preventing costly respins and field failures Deliver mathematically proven correctness guarantees on critical control logic, protocol interfaces, and safety-critical paths that customers depend on Reduce verification closure time by proving entire classes of behavior exhaustively, instead of writing thousands of constrained-random tests Build a library of reusable formal testbench components and assertion IP that accelerates bring-up on future blocks and projects Raise the formal verification capability of the team by teaching engineers how to think in properties, not just in tests Improve design quality upstream by surfacing ambiguous specifications and unintended corner cases early, before RTL is frozen Enable faster design iteration by providing rapid feedback on whether a proposed RTL change breaks proven invariants What You'l