Post-Silicon Validation, Senior Staff Engineer

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the lab where silicon meets reality, where the design that looked perfect in simulation sometimes does something completely unexpected at power-on, and you have learned to love that moment. Not because it is easy, but because finding the answer requires the kind of deep technical thinking that most people avoid. You are the engineer who gets called when a customer's chiplet link will not train and no one else can figure out why. You do not panic. You methodically work through the protocol stack, the package channel, the firmware state machine, and the on-die instrumentation until you isolate the variable that matters. You write code that performs reliably in an R&D lab, including when rapid development is needed to unblock critical debug. You balance speed with sound software engineering, knowing when a focused debug script is appropriate and when the solution requires maintainable, well-structured code that can evolve over time. Python for automation, C++ for performance-critical control loops, and you know when to reach for which one. You have architected software frameworks that other engineers depend on, and you take that responsibility seriously because bad infrastructure creates bad data. Working with customers does not intimidate you. You have debugged silicon in someone else's lab, explained what you found to their engineering team, and left them confident that the issue is understood and fixable. At Synopsys, you will set the technical direction for UCIe validation, mentor engineers who want to become you, and solve problems that matter to the future of chiplet-based systems. What You'll Be Doing Own the post-silicon electrical validation and characterization strategy for UCIe die-to-die interface IP, from test plan definition through silicon sign-off, determining what gets measured, how it gets measured, and what constitutes a pass Architect and develop the software solutions the team uses for lab automation, result processing, and silicon debug, spanning Python, C, and C++, including frameworks that handle instrument control, data capture, and automated test execution Lead complex debug efforts that span circuit design, package and interposer channel behavior, link training firmware, and protocol layer interactions, driving issues to root cause when the failure mode is ambiguous and the data is incomplete Support customers directly with the bring up and debug of their silicon, including sideband and mainband link training, lane repair and reversal, degraded mode operation, and chiplet interoperability, delivered through on-site lab visits and remote correlation sessions Develop characterization methodology for die-to-die links where direct probe access is limited, making effective use of on-die instrumentation, eye margining, built-in monitors, and traditional bench equipment like oscilloscopes, BERTs, and spectrum analyzers Design and develop UIs and data presentation tools used for customer evaluations, marketing demonstrations, and internal reporting, ensuring that complex silicon behavior is communicated clearly to technical and non-technical audiences Review and approve the work of other validation engineers, provide technical mentorship and coaching to junior and mid-level team members, and establish the measurement and correlation methodology the broader team adopts The Impact You Will Have Ensure the reliability and performance of Synopsys' UCIe die-to-die interface IP, directly contributing to the success of the multi-die and chiplet-based systems our