Post-Silicon Validation, Principal Engineer

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent a decade or more bringing silicon to life, and you know that the hardest problems do not show up in simulation. They show up in a customer's lab when the link will not train and nobody can explain why. You are the person who can connect observations across the analog, digital, protocol, package, and system domains, identify the most likely failure mechanisms, and drive the investigation to a defensible conclusion. When others see isolated symptoms, you see the larger technical story. You do not wait for perfect data. You work with what the silicon gives you, build the instrumentation to see what matters, and make the call on whether it ships. You have debugged enough high-speed links to know when the problem is in the analog, the protocol layer, the channel, or the way the customer assembled their interposer, and you can move between those domains without losing the thread. You write code because you have to. Not toy scripts, real validation frameworks in Python that other engineers depend on to characterize hundreds of test cases across process corners and data rates. You care about measurement integrity the way some people care about code coverage, because you have seen what happens when a team ships on bad data. At Synopsys, you will define how we validate UCIe die-to-die IP, own the silicon sign-off decision, and be the technical authority customers call when their multi-die product is stuck. What You'll Be Doing Define the post-silicon validation and characterization strategy for UCIe-based die-to-die interface IP, including the methodology, coverage models, and sign-off criteria that determine whether silicon is ready to ship Act as the final technical escalation point for silicon issues where root cause is not evident from the data, requiring you to evaluate intangibles across analog circuit behavior, package and interposer channel effects, link training firmware, protocol layer state machines, and system integration constraints Lead the bring up and debug of customer silicon, working remotely or sometimes on-site in customer labs to resolve sideband and mainband link training failures, lane repair and reversal issues, degraded mode operation, and chiplet interoperability problems Own the architecture and technical direction of the validation software platform in Python, including lab automation frameworks, data infrastructure, measurement correlation engines, and the instrumentation the organization depends on Establish how die-to-die links are characterized when direct probe access is limited or unavailable, defining the use of on-die instrumentation, eye margining techniques, built-in monitors, and the correlation of that data back to bench measurements and simulation results Drive validation programs that span multiple related areas of the business, coordinating across analog design, digital design, firmware, product engineering, applications, and marketing to reach shared technical outcomes and silicon readiness milestones Represent Synopsys in technical engagements with major customers and, where appropriate, in industry and standards forums such as the UCIe Consortium The Impact You Will Have Resolve the class of silicon problems that would otherwise stall a program or delay a customer's multi-die product launch, directly affecting time-to-market and revenue outcomes Raise the technical capability of the entire validation discipline through the methodology, tooling, and measurement standards you establish and the engineers you coach Shape how the organization and in