Technical Lead Manager, Machine Learning, Memory Subsystem Design

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As Technical Manager for TPU DRAM, you will develop and validate high performance memory subsystems for upcoming machine learning products. In this role, you will provide guidance to a team of design and verification engineers, collaborate with cross-functional peers on its system level aspects, and interact with the larger DRAM ecosystem, including DRAM manufacturers and third party IP providers. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $240000 - $333000 (USD) + 25% bonus target + equity + benefits Learn more about benefits at Google . Lead, mentor and manage a team of RTL Design and DV Engineers developing DRAM subsystems including HBM. Collaborate closely with the cross-functional teams (e.g., Design for Test, Signal/Power Integrity, Packaging, Physical Design, Software, Silicon Validation, Silicon Engineering) to plan and execute throughout the development cycle. Interface with third party IP providers of memory related IP including controllers, physical layers, and verification models during the selection and implementation phases of projects. Interface with DRAM manufacturers during the design and validation of DRAM subsystems. Drive improvements in design methodologies, processes, and quality control measures. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 15 years of experience in semiconductor design or design verification. 6 years of experience in people management, developing employees. Experience in designing or verifying DRAM-based memory subsystems. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience in creating and validating HBM-based memory subsystems.