ASIC Digital Design, Sr Staff Engineer-19314

** The hiring manager is open to both Markham and Mississauga locations** We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are A motivated and innovative ASIC digital verification engineer with relevant experiences. Working as part of a highly experienced mixed-signal design team, the candidate will be involved in verifying current and next generation Backplane Ethernet, PCIe, SATA, and USB SERDES products. The position offers an excellent opportunity to work with an expert team of digital and mixed signal engineers responsible for delivering high-end mixed-signal designs from creating test plans to performing functional and performance tests on the test-chips/products. What You'll Be Doing * Creating and updating test plans and test cases * Writing modular constrained-random/coverage driven Verilog, SystemVerilog * and UVM/VMM testbenches * Writing SystemVerilog assertions * Monitoring simulation regressions and debugging RTL and Gate level simulation failures * Writing functional coverage and performing functional/code/assertion coverage analysis * Tracking/Reporting issues in Jira and documenting in Confluence What You'll Need * BS/MS in Electronics / Electrical Engineering or related fields with 8+ years of industry experience with digital verification methodology such as VMM/UVM * Solid experience in writing testcases in Verilog and System Verilog * Solid experience in debugging complex testbench and design related issues * Knowledge of high-speed digital & mixed-signal design * Solid understanding of digital circuit design * Basic understanding of C/C++ and RISC processors * Familiarity with scripting languages (Python or Perl) * Self learner/independent, good organization and communication skills Skills desired: * System Verilog Assertions / formal verification * Good organization and communication skills The Impact You Will Have Catch critical bugs before tapeout that would otherwise cost months of schedule and significant silicon respins Enable faster time-to-market for high-speed SerDes IP used in data center, automotive, and consumer products worldwide Build reusable verification infrastructure that accelerates future product development and reduces verification cycle time Improve coverage closure rates and regression stability, giving the team confidence to tape out on schedule Mentor and influence verification methodology across the IP team, raising the bar for testbench quality and debug efficiency Contribute to the success of mixed-signal products that power connectivity in millions of devices Help shape verification strategy and tooling decisions that affect how the entire team works Who You Are You can look at a failing waveform with 50 signals toggling and zero in on the two that matter within minutes, not hours You write testbenches that someone else can pick up six months later and actually understand what you were testing and why You push back when a test plan is missing coverage for a critical corner case, and you do it in a way that makes the design team want to work with you You are comfortable working across disciplines, talking to analog designers about settling time and digital architects about protocol compliance without losing the thread You stay organized when managing multiple test plans, regression failures, and coverage gaps at once, and you know which fire to put out first You learn new protocols, tools, and verification techniques without needing a formal training plan, you read the spec, try it, and figure it out The Team You'll Be Part Of You will work as part of a highly experienced mixed-signal design and ve