Staff Applications Engineer, Synthesis and Formal Verification

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of ASIC design, and you know that the cleanest RTL and the best synthesis settings mean nothing if the customer cannot actually use them. You have debugged enough late-stage timing failures to recognize the synthesis decision that caused it three weeks earlier, and you care enough to prevent that from happening again. You do not just answer questions, you ask the ones that uncover what the customer actually needs versus what they think they need. You are comfortable sitting with a design team during a tapeout crunch, isolating a Formality proof failure that has blocked signoff for two days, and walking out with a fix and a plan to prevent it next time. You know the difference between a synthesis flow that demos well and one that scales across a 50-million-gate SoC with 12 voltage domains and conflicting timing constraints. You have opinions about clock gating, hierarchy, and physical-aware optimization, and you can defend them with data. At Synopsys, you will work directly with the semiconductor teams building the chips that power everything, and what you recommend will show up in silicon. What You'll Be Doing Own technical relationships with customer RTL, synthesis, formal verification, and physical design teams from flow evaluation through tapeout, serving as their trusted technical partner for Synopsys synthesis and equivalence checking products Debug complex synthesis and Formality issues reported by customers, reproduce problems in your own environment when possible, isolate root causes, and deliver clear recommendations or escalate to R&D with well-documented test cases Guide customers on RTL-to-netlist methodology using Fusion Compiler, Design Compiler, RTL Architect, and Formality, including advice on hierarchy, datapath optimization, physical-aware synthesis, clock gating, multi-bit registers, and handoff to place-and-route Analyze synthesis results, timing reports, constraint files, library characterization, and PPA outcomes to explain design behavior, identify optimization opportunities, and improve correlation with downstream implementation Create and maintain reusable scripts, reference flows, application notes, debug guides, and training materials that scale across customer programs and can be shared with global applications teams Translate recurring customer challenges and feature requests into clear use cases and product feedback for Synopsys R&D, and validate fixes and enhancements in real customer contexts Support technical evaluations, benchmarks, design reviews, and adoption of new synthesis and formal verification technologies across customer design teams The Impact You Will Have Customers will ship complex SoCs on schedule because you helped them resolve synthesis and equivalence checking issues that would have blocked tapeout Design teams will achieve better power, performance, and area outcomes because you identified RTL, constraint, or methodology improvements they could not see on their own Synopsys products will become more robust and easier to deploy because you brought field observations back to R&D as reproducible test cases and actionable feature requests Customer synthesis flows will scale and stabilize across programs because you built reference methodologies, scripts, and documentation that teams can reuse without starting from scratch Engineers at customer sites will trust Synopsys as a technical partner, not just a vendor, because you showed up during the hard problems and helped them solve it Your colleagues across global