Senior Power Integrity Engineer, Platforms Infrastructure

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Power Integrity Engineer within Platforms Infrastructure Engineering, you will play a pivotal role in developing one of the world's fastest-growing computing infrastructures. Working with a collaborative and high impact team, you will design, analyze, validate, and deliver robust and innovative power delivery network solutions at the chip, package, board, rack, and team levels. Your work will directly shape our next generation AI hardware for AL/ML, server, networking, and storage applications. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $159000 - $230000 (USD) + 15% bonus target + equity + benefits Learn more about benefits at Google . Design system-level power delivery network solutions across silicon, substrate packaging, and Printed Circuit Boards (PCBs). Partner with cross-functional teams to balance performance, cost, reliability, and availability trade-offs. Perform power integrity design validation, correlation studies, and root-cause analyses. Lead the triage and resolution of power integrity issues. Drive technology explorations into advanced power regulation and distribution, pioneering innovations across PCBs, chip packaging, and silicon. Engage with power module suppliers and industry partners to drive the development and evaluation of emerging power delivery technologies. Collaborate with EDA vendors to enhance simulation capabilities and methodologies. Minimum qualifications: Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience. 4 years of experience working in a system-level power delivery network design, analysis, and validation technical environment. Experience with PCB, package and silicon technologies, and their impact on power delivery solutions. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering, Physics, or a related field. 1 year of experience in technical leadership. Experience in board, substrate package, and on-chip power integrity/conversion design for FPGAs, ASICs, or high performance processors. Experience with industry-standard tools including Ansys (HFSS, Q3D, SIwave), Cadence (PowerSI/DC, Allegro, APD), CST, Keysight ADS, and Synopsys Hspice. Experience in system-level PDN modeling, switching regulators, and data center motherboard power design, advanced voltage regulators, and next-gen components. Experience in die-to-PCB hardware validation and correlation, with the ability to script and automate lab measurements and EDA simulation workflows.