Applications Engineering, Staff Engineer

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical design, where the difference between a chip that tapes out on schedule and one that slips six months often comes down to a decision you made about placement strategy or a script you wrote at 2am to analyze a timing path. You know that implementation is not about following a recipe, it is about understanding the tradeoffs deeply enough to know when to break the rules. Walking into a customer site two weeks before tape-out with a design failing timing does not rattle you. You have been there before. You know how to triage, where to look first, and how to communicate what is actually fixable versus what needs a hard conversation with management. You write TCL and Python that solves real problems, not just demos well, and you care that someone else can read and modify your code six months later. At 7nm and below, you understand that every decision has second-order effects. FinFET behavior, multi-patterning constraints, electromigration limits, these are not abstract concepts to you, they are the daily reality of getting a design to close. You have learned to balance PPA targets against schedule pressure and resource constraints, and you can explain those tradeoffs clearly to both the engineer debugging a clock tree and the director who needs to know if the project is still on track. What You'll Be Doing Support customer engagements on advanced-node designs at 7nm, 5nm, and below using Fusion Compiler and ICC2, helping engineering teams hit PPA targets under real schedule and resource constraints Develop and enhance physical design methodologies and automation solutions using TCL, Python, and Perl to improve design quality, predictability, and team efficiency across the RTL-to-GDS flow Debug complex physical design challenges including placement, clock tree synthesis, routing, timing closure, and power optimization on FinFET designs with multi-patterning and electromigration constraints Build and deliver methodology recommendations tailored to customer design constraints, process technologies, and project timelines, not generic best practices but solutions that fit their specific context Contribute to AI-assisted and machine learning-driven design optimization initiatives, applying data-driven approaches to solve implementation challenges that traditional methods struggle with Collaborate with R&D, product management, and field teams to translate customer pain points into product requirements and feature enhancements that make it into the next release Travel to customer sites as needed to provide onsite support, training, and design reviews, often under tight deadlines and high-stakes tape-out pressure The Impact You Will Have Enable customers to achieve timing closure and tape-out success on advanced-node designs that define next-generation AI, mobile, and datacenter products Build automation and methodology improvements that get reused across multiple customer engagements, multiplying your impact across dozens of designs Shape the roadmap of Synopsys physical design tools by feeding real customer challenges directly into R&D, influencing features that thousands of engineers will use Reduce design cycle time and improve PPA outcomes for customers working at the cutting edge of semiconductor technology, where every percentage point of performance or power matters Mentor field teams and customers on advanced physical design techniques, raising the bar for how complex designs get implemented across the industry Help drive adoption of AI-driven optimizat