Senior Staff Engineer, Custom IC Layout

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of custom layout, where a single misplaced contact can derail a tapeout and where DRC clean means nothing if the circuit doesn't perform. You know the difference between a layout that works on paper and one that survives across process corners, and you have debugged enough blocker issues at 2am to understand what customers actually need when they say 'it's urgent.' You are equally comfortable sitting with a foundry layout team walking through a migration flow as you are sitting with R&D explaining why a specific customer design rule is breaking their methodology. You do not just escalate problems, you own them until they are resolved, whether that means writing a SKILL script, building a workaround, or getting on a plane. Migration work excites you because it is never clean. Node-to-node and fab-to-fab analog IP migration means dealing with incomplete PDKs, shifting design rules, and customers who need it working yesterday. You have done this before and you know how to build flows that actually scale beyond the first test case. At Synopsys, you will work directly with the largest semiconductor companies in Korea on the most advanced nodes in production today. What you enable will ship in products that matter. What You'll Be Doing Own Custom Compiler technical engagement at leading Korean foundry, memory, and fabless customers, driving tool deployment, methodology adoption, and advanced-node enablement on their most critical custom layout projects Lead on-site debug and root-cause analysis for blocker issues, working directly with customer layout teams and Synopsys R&D to deliver patches, workarounds, and hotfixes aligned to customer tapeout schedules Develop and validate node-to-node and fab-to-fab analog IP migration methodologies, building production-ready flows that scale across multiple process nodes and customer design environments Drive adoption of layout synthesis using ASO.ai and other Synopsys.ai solutions, integrating them into customer workflows and proving out ROI on real customer designs Build and deliver methodology decks, application notes, training materials, and customer-facing workshops that translate complex tool capabilities into actionable flows for layout engineers Validate new Custom Compiler features on customer reference designs at advanced nodes, providing feedback to R&D on what works, what breaks, and what needs to change before general release Partner with field application teams and R&D to define product roadmap priorities based on direct customer engagement, ensuring that what we build next is what these customers actually need The Impact You Will Have Enable leading Korean foundry, memory, and fabless customers to adopt Custom Compiler and layout synthesis on their most advanced nodes, directly accelerating their time to tapeout and reducing manual layout effort Unblock critical customer tapeouts by resolving tool and methodology issues that would otherwise delay production schedules by weeks or months Build migration flows that allow customers to reuse analog IP across nodes and fabs, protecting millions of dollars in prior design investment and reducing redesign cycles Shape the Custom Compiler product roadmap by feeding real customer requirements and pain points directly into R&D, ensuring that future releases solve the problems that matter most to our largest accounts Establish Synopsys as the trusted technical partner for custom layout at Korea's leading semiconductor companies, strengthening customer relationships and dr