Staff Product Engineer - Physical Verification

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years deep in the trenches of physical verification, and you know that a clean signoff is never just about running a deck. It is about understanding what the foundry actually meant in that spec, what the customer is trying to build, and where the tool will break if you do not catch it first. You have debugged enough DRC violations and LVS mismatches to know that the answer is rarely in the error message. It is in the layout, the process node quirks, or a rule interpretation that nobody wrote down. You are comfortable sitting with a customer's design team, walking through a tapeout blocker, and leaving with a plan that works. You do not wait for perfect documentation. You read the foundry PDK, test it in ICV or Calibre, script a solution in Python or TCL, and move. You have a point of view on how verification flows should scale, and you are not afraid to push back when a methodology does not make sense or a release timeline is built on hope instead of reality. At Synopsys, you will work directly with the semiconductor companies building the next generation of chips, and what you deliver will determine whether they tape out on time or spend another month in verification hell. What You'll Be Doing Review customer and foundry specifications to develop, enhance, and maintain ICV rule decks and methodologies for DRC, LVS, PERC, ESD, and other physical verification requirements Serve as the primary technical interface between customers, foundries, R&D, and product engineering teams to translate requirements, drive feature implementation, and resolve complex verification issues Lead project planning and execution by aligning resources, schedules, risks, and deliverables to achieve high-quality releases and meet customer tapeout milestones on time Drive continuous improvement of tools, runsets, and verification methodologies through automation, scripting in Python, TCL, Perl, or Shell, and scalable development frameworks Provide technical leadership by making architectural decisions, proposing solutions for advanced node and 3DIC challenges, conducting technical reviews, and mentoring team members Conduct technical presentations, workshops, training sessions, and product demonstrations to promote best practices and advanced verification methodologies to customers and foundries Collaborate across Synopsys product teams to evaluate, validate, and deploy new ICV features that enhance runset quality, improve productivity, and ensure interoperability across the signoff ecosystem The Impact You Will Have Enable successful customer tapeouts by delivering high-quality physical verification solutions and signoff methodologies that actually work under real-world design constraints Accelerate customer productivity through optimized verification flows, automation, and scalable runset development practices that reduce turnaround time Strengthen customer and foundry partnerships through technical leadership, responsive support, and trusted execution that makes you the go-to engineer when things get hard Drive adoption and expansion of Synopsys physical verification technologies across advanced node, 3DIC, HBM, ESD solutions, and emerging semiconductor designs Influence product direction and future innovations through customer feedback, technology assessments, and cross-functional collaboration with R&D and product management Improve quality, scalability, and release predictability by establishing robust development processes and driving strategic enhancements across products and methodologies What You'